About Rain:

At Rain AI, we’re creating a future with abundant and scalable artificial intelligence. We're building the world’s most cost and energy efficient hardware for AI. Our products achieve an order of magnitude improvement over the status quo by co-designing every layer of the AI stack, from circuits to algorithms. Our ultimate goal is to become the dominant hardware company of the AI era.

Rain AI is currently a Series A stage startup and backed by world leaders in AI. Our seed round was led by Sam Altman (Open AI). In addition, our current VC partners include Y Combinator, Daniel Gross, Jaan Tallinn, Founders X Fund, Airbus Ventures, Liquid 2 Ventures and Deepwater.

About the role:

The Research Scientist Intern, AI HW/SW Co-Design (PhD) will contribute to developing a framework for an in-memory compute AI accelerator to perform hardware/software co-design and optimization. This framework will guide the architecture and algorithm design to optimize Rain’s hardware. This is a collaborative role – as an intern, you will have the opportunity to work across many teams at Rain.

This is a remote internship opportunity – you can work anywhere in the US. The anticipated start date for this internship would be Winter/Spring 2024 (flexible) with an ideal length of at least 4 months.

Responsibilities:

Lead and contribute to the HW/SW co-optimization of Rain’s AI accelerators, including but not limited to:

• Create functional models for Rain’s chips.
• Develop an HW/SW codesign framework.
• Optimize hardware architecture for Rain’s benchmarking suite.
• Develop new models for Rain’s next-generation hardware.
• Collaborate with the algorithms team to develop hardware-aware algorithms.
• Document and present results.

Required Qualifications:

• Currently pursuing a PhD in Computer Engineering, electrical engineering or a related field.
• Strong Knowledge of computer architecture and AI accelerator architecture.
• Experience with hardware models for accelerators and RISC-V processors.
• Experience with DNN models mapping to hardware.
• Experience with hardware-software co-design and design space exploration.
• Experience in developing and debugging in C/C++, Python and/or PyTorch.
• Excellent communication skills.

Preferred Qualifications:

• Publications in top conferences on computer architecture and design automation conferences or related topics.

This is position will be paid hourly. The anticipated hourly rate for this role is $45 to $85/hour.