About Rain:

At Rain AI, we’re creating a future with abundant and scalable artificial intelligence. We're building the world’s most cost and energy efficient hardware for AI. Our products achieve an order of magnitude improvement over the status quo by co-designing every layer of the AI stack, from circuits to algorithms. Our ultimate goal is to become the dominant hardware company of the AI era.

Rain AI is currently a Series A stage startup and backed by world leaders in AI. Our seed round was led by Sam Altman (OpenAI). In addition, our current VC partners include Y Combinator, Daniel Gross, Jaan Tallinn, Founders X Fund, Airbus Ventures, Liquid 2 Ventures and Deepwater.

About the role:

We’re looking for an experienced ML Hardware Architect to help define the architecture of Rain’s next-generation AI accelerators! This person will report to our Lead Architect.

This is a remote role, so you can work from anywhere in the United States.

Responsibilities:

• Provide technical leadership to the architecture team in the development of next-generation AI accelerators to enable novel online learning algorithms
• Work closely with the algorithms teams to understand and evaluate local and global data movement in systolic and data-flow architectures. Lead development of architecture simulators for system design, verification, prototyping and hardware-software co-optimizations
• Work closely with the IC Design lead to evaluate digital and mixed-signal design collaterals in synchronous and asynchronous architectures and hand-off architecture specifications to the IC Design team
• Work closely with the system software team to develop compilers and ISA extensions to enable new hardware functional units in an SoC setting
• Integrate proprietary accelerators and design macros with standard service cores.

Qualifications:

• MSEE with 10+ years or PhD in Electrical Engineering and/or Computer Engineering with a focus on SoC architecture design, accelerator designs, system modeling and simulation
• Deep understanding of core microarchitectures including x86, ARM and/or RISC V.
• Strong understanding of memory management schemes, on-chip and off-chip data movement, logic-memory optimizations and efficient code placement techniques,
• Experience with System Verilog, Python, C/C++ and the ability to write production-ready, annotated code
• Experience designing state-of-the-art data flow, spatial and systolic architectures and ability to integrate synchronous and asynchronous design macros with both digital and mixed-signal circuit collaterals.
• Familiarity with compiler optimizations, synthesis, code generation, programming models and computer architecture
• Familiarity with the integration of novel accelerators and design macros with service cores
• Familiarity with algorithmic techniques for on-device learning (online/continuous learning)
• Developed the dataflow architectures of at least two state-of-the-art AI accelerator macros
• Familiarity with deep learning models and willingness to learn novel algorithms and translate them into specifications for hardware accelerators
• Exhibit a high degree of motivation and independence
• Strong communication skills, both written and verbal

Preferred qualifications:

• PhD in Electrical Engineering and/or Computer Engineering with focus on near- and in-memory computing architectures for AI acceleration
• Demonstrated track record of owning architecture of an AI accelerator from conception to tapeout. Demonstration of programmability.

Our Benefits:

• Medical Insurance with 100% coverage of employee premiums
• Dental and Vision Insurance
• 401k match
• Unlimited PTO + all federal holidays
• Company wide time off: Time between Christmas and New Years, week of the 4th of July off
• Work from anywhere in the United States
• And more!

The anticipated annual base salary for this position in the United States is $220,000 to $320,000. This range does not include any other compensation components or other benefits that an individual may be eligible for.