Lead DFT Engineer
Rain Neuromorphics
San Francisco, CA, USA
Posted on Saturday, August 24, 2024
About Rain:
At Rain AI, we’re creating a future with abundant and scalable artificial intelligence. We're building the world’s most cost and energy efficient hardware for AI. Our products achieve an order of magnitude improvement over the status quo by co-designing every layer of the AI stack, from circuits to algorithms. Our ultimate goal is to become the dominant hardware company of the AI era.
Rain AI is currently a Series A stage startup and backed by world leaders in AI. Our seed round was led by Sam Altman (OpenAI). In addition, our current VC partners include Y Combinator, Daniel Gross, Jaan Tallinn, Founders X Fund, Airbus Ventures, Liquid 2 Ventures and Deepwater.
About the role:
Rain AI is looking for a DFT engineer to lead the architecture and implementation of DFT features for our AI accelerators. The candidate will report directly to Rain AI’s head of hardware engineering. The role involves defining the DFT requirements and architecture, all the way through implementation, verification, pattern generation and silicon characterization.
Responsibilities:
At Rain AI, we’re creating a future with abundant and scalable artificial intelligence. We're building the world’s most cost and energy efficient hardware for AI. Our products achieve an order of magnitude improvement over the status quo by co-designing every layer of the AI stack, from circuits to algorithms. Our ultimate goal is to become the dominant hardware company of the AI era.
Rain AI is currently a Series A stage startup and backed by world leaders in AI. Our seed round was led by Sam Altman (OpenAI). In addition, our current VC partners include Y Combinator, Daniel Gross, Jaan Tallinn, Founders X Fund, Airbus Ventures, Liquid 2 Ventures and Deepwater.
About the role:
Rain AI is looking for a DFT engineer to lead the architecture and implementation of DFT features for our AI accelerators. The candidate will report directly to Rain AI’s head of hardware engineering. The role involves defining the DFT requirements and architecture, all the way through implementation, verification, pattern generation and silicon characterization.
Responsibilities:
- Defining overall DFT architecture including scan, BIST and hard IPs
- Custom BIST development for CIM IP
- Implementation and verification of various DFT components in Verilog
- Defining DFT methodology for scalability
- ATPG verification, pattern generation and debug
- 10+ years of DFT experience with a minimum of Masters degree in electrical engineering
- Strong understanding of digital design concepts and testability principles
- Knowledge of scan design, boundary scan, BIST, and ATPG
- Experience with industry ATPG and BIST tools
- Familiarity with Verilog and some scripting languages like Python
- Excellent problem-solving skills and attention to detail
- Strong communication and teamwork skills
- Track record of taking silicon to production
- Medical Insurance with 100% coverage of employee premiums
- Dental and Vision Insurance
- 401k match
- Unlimited PTO + all federal holidays
- Two weeks off around Christmas and New Years
- Summer “shutdown”: one week-off for all employees
- Work from anywhere in the United States
- $500 of office equipment per year
- And more!